The continually increasing demand for high-speed data transmission, together with the continually increasing speeds of central processors, requires the development of low-latency, high-speed data links. Use of low-speed and high-latency data links in modern systems often results in bottlenecks to performance originating in the data links.
Not only are high-speeds and low-latencies required for modern data transmission, performance in a wide variety of physical conditions is also critical. For example, starting in 2004, the serial link-based PCI Express interconnect will be deployed as a replacement to today's PCI bus in chip-to-module, and board-to-board and backplane connections. The PCI Express specification defines a raw data rate of 2.5 gigabits per second (Gbps). The PCI Express roadmap anticipates up to 32-lane wide interfaces and faster (5.0 Gbps) connections. The XAUI serial-link interface is primarily intended for module and board connections in 10 Gbps Ethernet systems. XAUI supports a 3.125 Gbps per pin raw data rate on four transmit and four receive lanes. Since it is defined to drive 20 inches over FR4-based boards with two connectors, XAUI links are starting to be used for backplane connections. The InfiniBand™ switch-fabric architecture is targeted to connected server clusters and server blades in data centers. It supports a 2.5 Gbps wire-speed connection with 1-, 2- or up to 12-wire link widths, over copper, fiber and cable connections. Thus, although a number of interconnection standards for serial links exist, they share in common demands for high-speed (more than 2 Gbps) data rates over wide varieties of transmission media.
Presently, backplanes using serial link technologies can reach speeds of approximately three Gbps. However, demand for port capacities of 40 Gbps and aggregate port capacities of 200 Gbps exist. Backplane environments are especially difficult to signal over. For example, backplane environments in high-speed WAN routers, enterprise and storage area network switches, blade servers and telecommunications equipment typically include, as part of the signaling path, vias, daughterboard-to-motherboard connectors, and meandering signal lines.
In the design of a data transmission system, a key design decision is the election of either a parallel or serial link structure. Generally, parallel data links enjoy low-latency. At the physical interface of the parallel bus, data is instantly available on each clock edge for load-store applications. Parallel data is available to the control functions inside the processor without going through serialization conversions or decoding. However, the low latency of parallel buses inflicts costs on a system design. The multiple data lines of the parallel bus must have traces matched in length and matched with the clock signal to minimize timing skew. This trace-matching wastes valuable real estate on a printed circuit board, may require extra board layers, and considerably complicates system-level design.
Serial links, in contrast, have historically enjoyed higher transmission rates at the expense of increased latency. Presently, serial links are able to support data rates of approximately three Gbps, across 20 inches of board and two connectors, and thus have become suitable for lowering the cost of board-to-board and chip-to-module connections. Recently, the traditional disadvantages of serial links, i.e. the additional die area and latency required for serializing-deserializing, encoding-decoding, and clock recovery of the symbol stream, have been mitigated by the development of compact, low-latency transceivers.
A key factor that impacts the costs of both parallel and serial data links is manufacturability. Traditionally, serial link transceivers have been regarded as difficult to implement, requiring mixed signal expertise, tuned integrated circuit (IC) processes and special care during the silicon design flow. For serial-link interfaces to be adopted in high-volume applications, they must be widely available in foundries using standard processes, and compatible with standard chip packages and board designs. Additionally, it is desirable that serial-link interfaces have a robust design, are easily manufactured in a high-yield process, and are interoperable with a wide variety of companion devices. Specifically, desirable features of a serial link include: ability to function in both low- and high-loss environments, adjustable voltage swing, tunable equalization coefficients, transparent functionality, and ability to choose the most appropriate signaling scheme on a channel-by-channel basis.
It is well-known that in high-speed signaling environments, traditional binary signaling, employing symbols that have one of two values, sometimes limits the achievable data transfer rate. Previous serial data links generally do not include the ability to select either a binary (non return to zero (NRZ) or 2-PAM) or a 4-level (4-PAM) pulse amplitude modulation signaling scheme to achieve the optimum signal to noise ratio and bandwidth for each channel in the system. One reason that few such systems have emerged is that, to achieve a particular data rate over a communications channel, a system that is capable of transmitting both 2-PAM and 4-PAM symbols while maintaining a transparent interface to application logic must be operable at both a first symbol rate (for 2-PAM symbols) and at a second symbol rate (for 4-PAM symbols), the second symbol rate being one-half of the first symbol rate. In this way, a total data rate of the serial data link would remain constant in both a first PAM mode and in a second PAM mode. Further, such systems would have to provide a multiplicity of clocks whose frequency depends on the PAM mode. This complexity, however, is not compatible with the large installed base of application logic.
Thus, there is a need in the art for a communications system that provides transparent, multi-PAM and binary serial data transmission and reception over a wide variety of different connectors, materials, and trace lengths. A transparent system would provide a constant interface for application logic irrespective of the PAM mode in which it operates, enabling compatibility with legacy application logic. Additionally, it is desirable that a communications interface be able to automatically determine the mode that can achieve the highest data rate for a particular physical channel. Desirable are interfaces capable of providing the mode so determined as a recommendation to the application logic employing the interface. Also desirable are interfaces capable of fully automatically configuring a communications channel for operation in the determined mode and optimally completing such configuration in a way that is transparent to the systems connected to the communications channel.
Like reference numerals refer to corresponding parts throughout the several views of the drawings.